In the previous tutorial, different types of registers were discussed. The registers and counters are two types of sequential circuits that are solely build from flip flops. The counters are those registers that go through predetermined sequence of states on the application of input pulses. The input pulses can be coming from a master clock or some external source. They may apply to the counter either at regular interval or randomly. There are two types of counters – Asynchronous counter (also known as ripple counter) and Synchronous counter.

The sequence of states in a counter can be either binary numbers or any other sequence of states. The counters that follow binary number sequence are called binary counters. The binary counters are again categorized as Up Counter, Down Counter and Up/Down Counter. Both Ripple and Synchronous counters can be used as binary counters. There are many other types of counters as well that follow different sequence of states other than the binary numbers like BCD counter, Ring Counter, Johnson Counter etc. Let us learn about each of these counters.

** Asynchronous/Ripple Counter** –

In Asynchronous or Ripple counter, input pulse is applied to one flip flop or some flip flops of the counter and their output drives the other flip flops one after the other. So, all the flip flops of a ripple counter do not share a common clock pulse, instead the clock pulse is applied to one or some flip flops only.

This is the simplest counter in terms of logical operation and is therefore the easiest to design. In this counter, all the flip-flops do not share a common clock signal. The clock pulse is applied to the first flip-flop. i.e. the least significant bit stage of the counter and the successive flip flop is triggered by the output of the previous and thus the counter has a cumulative settling time. Hence, its speed of operation is limited.

The first stage of the counter thus switches first on the application of a clock pulse to the first flip flop and the successive stage changes their states in turn causing a ‘ripple through effect’ of the count pulses. As the triggers move through the flip – flops like a ripple, this type of counter is called ripple counter. The ripple counter can be binary counter (in case it follows binary number sequence) or it can be constructed to follow other sequence of states like BCD ripple counter follows BCD numbering sequence.

** Synchronous Counter** –

In synchronous counters, a common clock pulse is applied to the inputs of all flip flops. All the flip flops are triggered by the common clock pulse simultaneously. In such case, the change in the state of a flip flop is determined by the data input to it instead of the application of the clock pulse. The clock pulse is usually generated from a master clock in a periodic fashion. The synchronous counters can also be constructed to either follow binary number sequence like in Binary Synchronous Counter or other sequence of states like BCD numbering system in case of BCD synchronous counter.

** Types of Binary Counters **–

The Binary Counters follow sequence of binary numbers. Depending upon the way in which the counting progresses, the ripple and synchronous binary counters are classified as follows –

1)** Up Counter **– Up counter progresses the counting in ascending order of binary numbers. The counting usually begins from 0 and progresses up to a fixed binary number. An n-bit up counter can count up to 2^{n} binary numbers. For example, 8-bit binary counter can count up from 0 to 255.

2) **Down Counter **– Down counter progresses the counting in descending order of binary numbers. The counting begins from a fixed binary number and progresses downward to 0. An n-bit down counter can count down from 2^{n} binary numbers. For example, 8-bit binary down counter can count down from 255 to 0.

3) **Up/Down Counter **– Up/Down Counter is constructed by combining Up and Down Counters. In Up/Down counter, a mode control (M) input is provided to select up or down mode. The mode control input involves a combinational circuitry which is used between each pair of flip flops in order to select up or down mode of counting. An n-bit up/down counter can count up or down 2^{n} binary numbers. For example, 8-bit up/down binary counter can count up or down binary numbers in range from 0 to 255.

** Ripple Binary Up Counter** –

A Binary Ripple Up counter progresses through states counting binary numbers in ascending order. Making this counter is very simple and it can be designed simply by applying clock pulse to one flip flop and cascading the output to the next flip flop. The subsequent flip flops in the counter are cascaded similarly. A 2-bit ripple up counter built using toggle (T) flip flops is shown below –

*Fig. 1: Ripple Binary Up Counter Logic Gate Diagram *

The JK flip flop can also used instead of T flip flops in the construction of this counter by connecting J and K inputs permanently to logic 1. In the 2-bit ripple up counter shown above, external clock is applied to the clock input of flip-flop A and QA output is applied to the clock input of the next flip-flop i.e. Flip Flop – B. This 2-bit ripple up counter counts from 00 to 11. Its operation can be summarized by the following function table –

From the function table, it can be seen that initially both the flip flops are in the reset state. So initially, Q_{B}Q_{A} = 00. Now the first negative clock edge is applied to the clock input of flip flop A. As soon as the first negative clock edge is applied, flip flop A is toggled and QA becomes equal to 1. QA is connected to clock input of flip flop – B. Since, QA has changed from 0 to 1, it is treated as the positive clock edge by flip flop B. There is no change in QB because flip flop B is a negative edge triggered flip flop. So, after the application of first clock pulse, QBQA = 01.

Next, the second negative clock edge is applied to the clock input of the flip flop A. On the arrival of second negative clock edge, flip flop A toggles again and QA is reset to 0. The change in QA acts as a negative clock edge for flip flop B. So it also toggles and QB is set to 1. Therefore, after the application of second clock pulse, QBQA = 10. Next, the third negative clock edge is applied to the clock input of flip flop A. On the arrival of third negative clock edge, flip flop A toggles again and QA is set to 1 from 0. Since this is a positive going change, flip flop B does not respond to it and remains inactive. So QB does not change and continues to be equal to 1. Therefore, after the application of third clock pulse, QBQA = 11. On the arrival of fourth negative clock edge, flip flop A toggles again and QA is set to 1 from 0. This negative change in QA acts as clock pulse for flip flop B. Hence it toggles QB from 1 to 0. Therefore, after the fourth clock pulse, QBQA = 00.

** Ripple Binary Up/Down Counter** –

In the Up/Down ripple counter, all the flip flops operate in the toggle mode. So either T flip-flops or JK flip-flops are used for its construction. The LSB flip-flop receives clock directly. But the clock to every other flip flop is obtained from output of the previous flip flop. The counter has mode control (M) input. Depending upon the current state of the mode control input, either up or down mode of counting is selected. The counter operates in the following two modes –

1) **Up Counting Mode (in case M=0)** − The Q output of the preceding flip flop must be connected to the clock of the next stage if up counting is to be achieved. For the selection of this mode, the mode select input M should be at logic 0 (i.e. M=0).

2) **Down Counting Mode (in case M=1) **− If the Mode Control Input is set to 1, then the Q bar output of the preceding Flip Flop is connected to the next FF. This will operate the counter in the down counting mode.

For example, consider 3-bit binary up/down ripple counter. Since, it is 3-bit ripple counter, its construction requires 3 flip flops. There is a mode control input that is essential to control selection of up or down counting mode. For a ripple up counter, the Q output of preceding Flip Flop is connected to the clock input of the next one. While, for a ripple down counter, the Q bar output of preceding Flip Flop is connected to the clock input of the next one. The 3-bit ripple Up/Down counter has the following circuit diagram –

*Fig. 2: Ripple Binary Up Down Counter Logic Gate Diagram*

The selection of Q and Q bar output of the preceding Flip Flop be controlled by the mode control input M such that, If M = 0, Up counting mode is selected. So, Q is connected to CLK. If M = 1, Down counting mode is selected. So, Q bar is connected to CLK. A 3-bit Up/Down Ripple Counter can be represented by the following block diagram –

*Fig. 3: Ripple Binary Up Down Counter Block Diagram *

The operation of this counter can be represented by the following function table –

From the function table, it can be seen that when Mode Control Input (M) is 0, Up counting mode is selected. If M = 0 and M bar = 1, then the AND gates 1 and 3 are enabled whereas the AND gates 2 and 4 are disabled. Hence Q_{A} gets connected to the clock input of Flip Flop B and Q_{B }gets connected to the clock input of Flip Flop C. These connections are same as those for the normal up counter. Therefore, with M = 0 the circuit work as an up counter. When Mode Control Input is 1, Down counting mode is selected. If M = 1, then AND gates 2 and 4 are enabled whereas the AND gates 1 and 3 are disabled. Hence Q_{A} bar gets connected to the clock input of Flip Flop B and Q_{B} bar gets connected to the clock input of Flip Flop C. These connections makes a down counter. Thus, with M = 1 the circuit works as a down counter.

** Ripple BCD Counter** –

BCD counter also known as decimal counter counts BCD numbers from 0 to 9. Since, the BCD numbers are 4-bit numbers, four flip flops are required to design a BCD counter. The counter follows a sequence of 10 states and counts from 0 (0000) to 9 (1001) returning back to 0 (0000). Several BCD counters can be connected in series to represent a larger decimal number. In such case, a BCD counter for each positional weight must be connected in the circuit.

A BCD counter can be constructed by using JK flip flops. For designing a BCD Counter, four flip flops are required. These flip flops can be represented by their binary weights as Q1, Q2, Q4 and Q8. The J and K inputs of the flip flops are either connected permanently to logic 1 or to the outputs of other flip flops. The output of flip flop Q1 is connected to clock input of both flip flops Q2 and Q8. The output of flip flop Q2 is connected to clock input of the flip flop Q4. The BCD counter constructed from JK flip flops has the following logic gate diagram –

*Fig. 4: Ripple BCD Counter Logic Gate Diagram *

The counter progresses counting from Q8Q4Q2Q1 = 0000 to Q8Q4Q2Q1 = 1001. The operation of the counter can be summarized by the following function table –

** Synchronous Up Counter** –

The binary up counter can also be designed as synchronous counter. The synchronous binary up counter has a common clock signal and the sequence of states depends on the data input to the flip flops. For example, to design a 2-bit synchronous counter, two flip flops are required. Let the flip flop storing LSB be A and flip flop storing MSB be B. The JA and KA inputs of Flip Flop A are tied to logic 1. So Flip Flop A works as a toggle flip-flop. The JB and KB inputs are connected to QA. The 2-bit synchronous binary up counter has the following logic diagram –

*Fig. 5: Synchronous Binary Up Counter Logic Gate Diagram*

Initially, both the Flip Flops are in the reset state. So initially, QBQA = 00. When the first negative clock edge is applied, Flip Flop A is toggled and QA changes from 0 to 1. But at the instant of application of negative clock edge, QA = JB = KB = 0. Hence Flip Flop B does not change its state. So, QB remains 0. So, after applying first clock pulse, QBQA = 01. When the second negative clock edge is applied, Flip Flop A toggles again and QA changes from 1 to 0. But at this instant QA remained 1. So JB = KB= 1 and Flip Flop B is toggled. Hence QB changes from 0 to 1. So, after applying second clock pulse, QBQA = 10.

When third negative clock edge is applied, Flip Flop A toggles from 0 to 1 but there is no change of state for Flip Flop B. So, after applying third clock pulse, QBQA = 11. When fourth negative clock edge is applied, QA changes from 1 to 0 as QB also changes from 1 to 0. So, after applying fourth clock pulse, QBQA = 00. The functioning of the synchronous 2-bit binary up counter can be summarized by the following function table –

** Synchronous Up/Down Counter** –

A Synchronous Count Down Counter can constructed using T Flip Flops by connecting complement outputs instead of normal outputs as in case of Up Counter. An Up/Down Counter can be constructed by placing a combinational circuitry between each flip flop to determine the counting mode. The combinational circuitry can be designed using AND gates and providing an additional mode control input (M) similar to done in case of Ripple Up/Down Counter.

** Synchronous BCD Counter** –

Again a BCD counter can be constructed as Synchronous counter. For building a synchronous BCD counter, both present and past states of flip flops need to be considered. The synchronous BCD counter follows the below function table –

From the above function table, the synchronous BCD counter has the following logic gate diagram –

*Fig. 6: Synchronous BCD Counter Logic Gate Diagram *

The BCD counter is also called decade counter. The counter counts BCD numbers 0 (0000) to 9 (1001). Since BCD numbers are 4-bit long, four flip flops are required to design the BCD counter. The Synchronous BCD counter has all the flip flops sharing a common clock pulse.

** Ring Counter** –

The ring counter is used for generating timing signals. The timing signals are required to control operations in a digital system. The ring counter is a circular shift register in which only one flip flop is set at a time while all others remain cleared. In such counter, a single bit is shifted from one flip flop to another producing a sequence of timing signals. For example, to produce four timing signals in a digital system, a 2-bit counter combined with a decoder circuit can be used as ring counter. The ring counter will have flip flops storing bits in the following sequence – 1000, 0100, 0010, 0001 and 1000.

** Johnson Counter** –

An n-bit ring counter shifts a single bit through the flip flops generating n number of sequence states. The number of states in a ring counter can be doubled by connecting flip flops in ring counter in a switch-tail manner. This can be done by connecting output of one flip flop with the next. This is called Johnson Counter. It has the following logic gate diagram –

*Fig. 7: Johnson Counter Logic Gate Diagram *

The operation of Johnson counter can be summarized by the following function table –

In the next tutorial, discussions related to digital memory will be done.

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